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SPMC802B SP
32-pin General Purpose 32 Microcontroller (OTP)
AUG. 07, 2002 Version 1.0
SUNPLUS TECHNOLOGY CO. reserves the right to change this documentation without prior notice. Information provided by SUNPLUS TECHNOLOGY CO. is believed to be accurate and reliable. However, SUNPLUS TECHNOLOGY CO. makes no warranty for any errors which may appear in this document. Contact SUNPLUS TECHNOLOGY CO. to obtain the latest version of device specifications before placing your order. No responsibility is assumed by SUNPLUS TECHNOLOGY CO. for any infringement of patent or other rights of third parties which may result from its use. In addition, SUNPLUS products are not authorized for use as critical components in life support devices/ systems or aviation devices/systems, where a malfunction or failure of the product may reasonably be expected to result in significant injury to the user, without the express written approval of Sunplus.
SPMC802B
Table of Contents
PAGE
1. GENERAL DESCRIPTION.......................................................................................................................................................................... 3 2. FEATURES.................................................................................................................................................................................................. 3 3. BLOCK DIAGRAM ...................................................................................................................................................................................... 3 3.1. CPU ..................................................................................................................................................................................................... 4 3.2. MEMORY ............................................................................................................................................................................................... 4 3.3. OSCILLATOR .......................................................................................................................................................................................... 4 4. SIGNAL DESCRIPTIONS ........................................................................................................................................................................... 5 4.1. PIN DESCRIPTIONS (32 PIN) ................................................................................................................................................................. 5 4.2. PIN ASSIGNMENT .................................................................................................................................................................................. 5 5. FUNCTIONAL DESCRPITIONS.................................................................................................................................................................. 7 5.1. PORT A GROUP ..................................................................................................................................................................................... 7 5.2. PORT B GROUP ..................................................................................................................................................................................... 7 5.3. PORT C GROUP..................................................................................................................................................................................... 8 5.4. PORT D GROUP..................................................................................................................................................................................... 9 5.5. INTERRUPT ............................................................................................................................................................................................ 9 5.6. TIMER1 & REAL TIME INTERRUPT ......................................................................................................................................................... 10 5.7. TIMER2 & PWM .................................................................................................................................................................................. 10 5.8. COMPARATOR ...................................................................................................................................................................................... 10 5.9. WAIT & STOP MODE.......................................................................................................................................................................... 10 5.10. RESET ...............................................................................................................................................................................................11 5.11. RESET MANAGEMENT REGISTERS ......................................................................................................................................................11 6. ELECTRICAL CHARACTERISTICS......................................................................................................................................................... 12 6.1. ITEM DEFINITION.................................................................................................................................................................................. 12 6.2. ABSOLUTE MAXIMUM RATING ............................................................................................................................................................... 12 6.3. RECOMMENDED OPERATING CONDITIONS............................................................................................................................................. 12 6.4. PIN ATTRIBUTE DESCRIPTION (VDD = 5.0V, TA = 0C~70C)............................................................................................................... 12 7. PACKAGE/PAD LOCATIONS ................................................................................................................................................................... 14 7.1. PACKAGE INFORMATION ....................................................................................................................................................................... 14 7.2. ORDERING INFORMATION ..................................................................................................................................................................... 25 8. DISCLAIMER............................................................................................................................................................................................. 26 9. REVISION HISTORY ................................................................................................................................................................................. 27
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SPMC802B
32-PIN GENERAL PURPOSE MICROCONTROLLER (OTP)
1. GENERAL DESCRIPTION
The SPMC802B is an OTP version of SPMC02A with reliability enhancement. It equips with an 8-bit Sunplus CPU core, 4.5K SPMC802B also Three groups of bytes of program ROM, and 128 bytes of RAM. Comparator inputs, and a Watchdog Timer. ! Three external interrupt groups, one is come from individual I/O Channel PB5 and group input PA3:0, one is come from individual I/O Channel, PA7, and one is a group input, PC port. ! External Reset input option on PB4. ! An 8-bit Timer with Real Time Interrupt control. ! An 8-bit Re-loadable Timer with 8 stages prescalar. ! One 6-bit PWM waveform output. ! Two voltage Comparator inputs with selectable internal or external voltage reference. compare result. An interrupt event control for the
combines with four I/O ports, two timers with one PWM output, two interrupt are implemented for different kinds of applications. Major application fields are small home appliances or computer peripheral applications. The details are described below.
2. FEATURES
! Built-in 8-bit Sunplus CPU core with two index registers and up to 6MHz clock operation. ! 28 general-purpose I/O channels that are belong to four I/O ports. Some of them are combined with the options to select Pull-Up/Down Resistors.
! A watchdog timer for program control. ! 4.5K bytes of ROM with 128 bytes of RAM. ! R-Oscillation or Crystal input options for system clock. ! Stop or Wait Control setting for Power-Saving Mode. ! Slow Transition Output Pins.
3. BLOCK DIAGRAM
XO/R XI VDD VSS OSC. CKT 4.5K bytes PROM $600~$FFF & $1800~$1FFF 128 bytes RAM $80 ~ $FF
8 - bit CPU
ADDRESS BUS DATA BUS
TIMER 1 & RTI & Watch_Dog timer
Interrupt Generator & RESET generator TIMER 2 & 6 bits PWM waveform generator I/O PORT & External CLOCK Pin I/O PORT & PWM waveform output I/O PORT & 2 set Comparator circuit
PA3-0 PA7 PC7-0
I/O PORT & External Interrupt I/O PORT & External RESET Pin I/O PORT & External IRQ Pin
/13
RESET(PB4)
PB6
/1
/1
IRQ(PB5) PA6 PB3-1 PD3-0
PB7 PA4,PA5 PB0
/1
/1
I/O PORT
/8
/3
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SPMC802B
3.1. CPU
The microprocessor of SPMC802B is a SUNPLUS high performance processor equipped with Accumulator, Program Counter, X Register, Y Register, Stack Pointer and Processor Status Register (The same as 6502 instruction`s structure). SPMC802B is a fully static CMOS design. application needs. The oscillation frequency could be varied up to 6.0MHz depends on the
3.2. Memory 3.2.1. Memory map
SPMC802B Supports 4.5K bytes of EPROM with 512 bytes test ROM. It also has the configurable options can be programmed The addresses for EPROM, by writer for different applications. $1800h ~ $1FFFh. $00FFh.
test ROM, and options are located in $0400h ~ $0FFFh and The RAM area is located in $0080h ~ A set of system control The functional control registers and I/O control registers
are located in $0000h ~ $0013h.
3.1.1. Block diagram of Sunplus CPU
REGISTER SECTION CONTROL SECTION RESET IRQ NMI
registers can be configured through indexed access addresses $003Eh and $003Fh. The buffers for stack pointer are started This area is mirrored to A system control register from $01FFh with downward direction. the RAM area $00FFh ~ $0080h.
RDY
INTERRUPT LOGIC
A0 A1 A2 A3 A4 A5 A6
INDEX REGISTER X
INDEX REGISTER Y
STACK POINT REGISTER S
INSTRUCTION DECODE
PD
named Stack Limit Register (SLR) is used to limit the Stack area to prevent the override of the normal operating contents in the RAM. Once the Stack is over the limiter, CPU reset will be generated. To prevent the illegal accesses on undefined addresses, there is a
ABL
ABH
LEGEND
= 8BIT LINE = 1 BIT LINE
A7
ALU
ADDRESS BUS
ACCUMULATOR A
TIMING CONTROL
qualification block to limit the accesses.
The illegal accesses will
PCL
A8 A9 A10 A11 A12 A13 A14 A15
PCH
INPUT DATA LATCH IDLI
PROCESSOR STATUS REGISTER P
generate the CPU reset to restart the program.
CLOCK GENERATOR
CLK 0 IN
R/W
DATA BUS BUFFER
INSTRUCTION REGISTER
3.2.2. NMI, Reset, IRQ vectors
The address of NMI (not provided in this chip), RESET and IRQ are located from $1FFA to $1FFF. The interrupt vectors should
D0 D1 D2 D3 D4 D5 D6 D7
DATA BUS
be specified in the program to have proper operation.
3.3. Oscillator
The SPMC802B supports AT-cut parallel resonant oscillated Crystal /Resonator, or RC oscillator, or external clock sources by configurable option (select one from those three types). design of application circuit should follow The the vendors` specifications or recommendations. below represents typical X'TAL/ROSC applications: The diagram listed circuits for most
SPMC802B XI XO/R
SPMC802B XI VDD XO/R
SPMC802B XI XO/R
20 pf
20 pf
Rosc
(b) RC Oscillator Connections
UNCONNECTED
External Clock
(a) Crystal or Ceramic Resonator Connections
(c) External Clock Source Connections
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SPMC802B
4. SIGNAL DESCRIPTIONS
4.1. PIN Descriptions (32 PIN)
Mnemonic VDD VSS XO/R PIN No. 28 27 4 System Power Supply. System Ground. Crystal In or Resistor In Input. An external resistive pull-up is used to connect with internal OSC It will circuitry for generating the internal clock and the related time base in R-Oscillation mode. be connected with external crystal for a crystal oscillation circuitry in crystal mode. XI 5 Crystal Output or External Clock Input. External clock input is used to connect with internal clock It will In circuitry to generate the internal clock and the related time base in External clock mode. be connected with external crystal for a crystal oscillation circuitry in crystal mode. PA7:0 9, 10, 11, 12 20, 21, 22, 23 PB5 (Vpp) PB1 (SCK) PB0 (SDA) PB7:6,4:2 19, 14, 6, 3, 30 PC7:0 PD3:0 32, 1, 17, 16 31, 2, 18, 15 8, 7, 26, 25 13 29 24 GPIO Port A7:0. Comparator. GPIO Port B5. General-purpose inputs/outputs. Using the internal setting can configure it. addition, PA7 can be used as the external interrupt input. General-purpose input/output. PA5:4 can be the compare inputs of In Functional Description
PA3:0 can be the group input of external interrupt. Using the internal setting can configure it. It is used as Programming Voltage In
addition, PB5 can be used as the external Main IRQ input. input in Programming mode. GPIO Port B1. GPIO Port B0. General-purpose input/output.
Using the internal setting can configure it.
addition, it is used as Serial Clock input in Programming mode. General-purpose input/output or the voltage reference input for the Comparator. In addition, it is used as Serial Data input/output in Using the internal setting can configure it. In Using the internal setting can configure it. Programming mode. GPIO Port B7:6,4:2. for Timer 2. GPIO Port C7:0. GPIO Port D3:0. General-purpose inputs/output. addition, PB7 can be the PWM waveform output. General-purpose inputs/outputs. General-purpose inputs/outputs. PB6 can be set as external event/clock input In
PB4 can be used as the Main nRESET input. Using the internal setting can configure it. Using the internal setting can configure it.
addition, these pins can be used as the external interrupt inputs.
4.2. PIN Assignment 4.2.1. 32 PIN package
28 VDD 27 VSS 26 PD1 25 PD0 32 PC7 31 PC3 18 PC1 17 PC5 30 PB2 29 PB1 24 PB5 23 PA0 22 PA1 21 PA2 20 PA3 19 PB7
4.2.2. 28 PIN package
24 VDD 23 VSS 28 PC7 27 PC3 16 PC1 PC0 13 15 PC5 PC4 14 26 PB2 25 PB1 22 PB5 21 PA0 20 PA1 19 PA2 18 PA3 PB0 11 17 PB7 PB6 12
SPMC802B
SPMC802B
PA6 10
PA5 11
PA4 12
PB0 13
PB6 14
PC0 15
PC4 16
XO/R
PC6
XO/R
PB4
PC6
PC2
PB3
PD2
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PD3
PA7
5
PC2
PB3
PA4 10
1
2
3
4
5
6
7
8 PA6
1
2
3
4
5
6
7
8
9
XI
PB4
PA7
PA5
XI
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PC2 PB3 XO/R XI PB4 PA7 PA6 PA5 PA4 PB0 10 PB6 11 PC0 12 9 8 7 6 5 20 VSS 19 PB5 18 PA0 17 PA1 16 PA2 15 PA3 14 PB7 13 PC1 4 21 VDD 3 22 PB1 2 23 PB2
1
24 PC3
PB3 XO/R XI PB4 PA7 PA6 PA5 PA4 PB0 PB6 10
11 PB7
1
2
3
4
5
6
7
8
9
12 PA3
20 PB2
19 PB1
18 VDD
17 VSS
16 PB5
15 PA0
14 PA1
13 PA2
Proprietary & Confidential
4.2.4. 20 PIN package
4.2.3. 24 PIN package
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SPMC802B
SPMC802B
6
XO/R XI PB4 PA7 PA6 PA5 PA4 PB0 4 5 6 7 8 3 2 1 16 PB1 15 VDD 14 VSS 13 PB5 12 PA0 11 PA1 10 PA2 9 PA3
PB3 XO/R XI PB4 PA7 PA6 PA5 PA4 PB0
1 2 3 4 5 6 7 8 9
18 PB2 17 PB1 16 VDD 15 VSS 14 PB5 13 PA0 12 PA1 11 PA2 10 PA3
4.2.6. 16 PIN package
4.2.5. 18 PIN package
SPMC802B
SPMC802B
SPMC802B
AUG. 07, 2002
Version: 1.0
SPMC802B
5. FUNCTIONAL DESCRPITIONS
SPMC802B is an OTP for SPMC02A emulating. blocks have two kinds of control input. configurable option. The functional I/O attribute. Setting the bit(s) to '1' will enforce the It is a write-only register. Reading PA will The first one is They Once corresponding pad(s) to output mode.
The other is programmable register.
PA is used to store the data contents for output.
Configurable options are used as permanent assignment. are configured with the program code in the same time. unchangeable as the program code. are described in detail later.
get the stored data when corresponding bit of DPA is set as output mode, or will get the pad status if it is in input mode. There is a built-in Pull-Up/Down resistor on each pad. have pull-up resistors that is permanent in SPMC802B. can be configured with pull-up or pull-down resistors. PA7:6 PA5:4 These
the configurable options are written to SPMC802B, they are The configurable options The program can Programmable registers are used to
control the functional blocks by the program.
access the registers to achieve the desire functions. There are two kinds of registers with different access methods. The first kind of registers uses direct access as normal. function. They are summarized as following. The second kind of registers uses indexed write access for specific All of the function registers will be set to 0 (except rt1 and rt0 in TCS1), when a reset signal occurred. signal occurred. The bits rt1 and rt0 will be set to 1 when a reset
configurable pull-up/down resistors should be selected or enabled by configurable option first, and then can be controlled by users' program through RPA. The output mode on PA7:6 can be programmed as slow transition outputs. Programming the bit slowe in RPA to '1' will enforce the output high to low transition time to 250ns 20% with 500pf pad loading at 2.0MHz CPU frequency. PA7 and PA3:0 are used as external interrupt inputs. The more They are
5.1. Port A Group
The I/O port A has 8 programmable I/Os that are controlled by data register PA, direction control register DPA, and pull-up/down resistance control register RPA. DPA is used to control the pad
details are described in section Interrupt.
PA5:4 are used as The more details
voltage compare inputs for Comparator function. analog inputs to provide source voltage inputs. are described in section Comparator.
The corresponding pads are assigned for SPMC802B as following: (VDD = 5.0V) PIN PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 Rp 5K Up Always 5K Up Always 100K Up/Down@rpa5 100K Up/Down@rpa4 100K Up/Down@rpa3 100K Up/Down@rpa2 100K Up/Down@rpa1 100K Up/Down@rpa0 IN Schmitt-Trigger Schmitt-Trigger OUT -/8mA -/8mA 8/8mA 8/8mA 8/8mA 8/8mA 8/8mA 8/8mA CMP1 compare input CMP0 compare input IRQ0 interrupt input IRQ0 interrupt input IRQ0 interrupt input IRQ0 interrupt input Special Function IRQ1 interrupt input
5.2. Port B Group
The I/O port B has 8 programmable I/Os that are controlled by data register PB, direction control register DPB, and pull-up/down resistance control register RPB. I/O attribute. DPB is used to control the pad It is a write-only register. Reading PB will Setting the bit(s) to '1' will enforce the There is a built-in Pull-Up/Down resistor on each pad except PB5. PB7, PB6, PB3, and PB0 can be configured with pull-up or pull-down resistors. These configurable pull-up/down resistors PB5 does not have PB4, should be selected by configurable option first, and then can be controlled by users' program through RPB. the internal resistor. For interrupt input on PB5, an external They can be controlled by
corresponding pad(s) to output mode.
PB is used to store the data contents for output.
get the stored data when corresponding bit of DPB is set as output mode, or will get the pad status if it is in input mode.
pull-up resistor is needed to maintain the interrupt function. PB2, and PB1 have pull-up resistors. users' program through RPB.
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SPMC802B
In SPMC802B, the output mode on PB2 and PB1 can be an open-drain pin with slow transition by program. To achieve the slow transition function, programming the bit slowe in RPA to '1' will enforce the output high to low transition time to 250ns 20% with 50pf pad loading at 2.0MHz CPU frequency. PB7 can be a PWM waveform output. clock or event input for Timer2. input with falling-edge trigger. PB6 can be an external PB5 is used as external interrupt PB4 can be used as external PB0 In case
active-low reset input by enabling the configurable option. can be reference voltage input for Comparator function. pull-up/down should be disabled. in related sections.
of using PB0 as external reference voltage input, the resistive The more details are described
The corresponding pads are assigned for SPMC802B as following: (VDD = 5.0V) PIN PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 Rp 100K Up/Down@rpb7 100K Up/Down@rpb6 No Pull-Up/Down 100K Up@rpb4 100K Up/Down@rpb3 100K Up@rpb2 100K Up@rpb1 100K Up/Down@rpb0 Schmitt-Trigger Schmitt-Trigger IN OUT 8/8mA 8/8mA -/8mA 8/8mA 8/8mA -/20mA -/20mA 8/8mA Comparator Vref input Special Function PWM waveform output External clock/event input IRQ0 interrupt input External nRESET input
5.3. Port C Group
The I/O port C has 8 programmable I/Os that are controlled by data register PC, direction control register DPC, and pull-up/down resistance control register RPC. I/O attribute. DPC is used to control the pad It is a write-only register. Reading PC will PC7:0 are used as external interrupt inputs. described in section Interrupt. The more details are Setting the bit(s) to '1' will enforce the There is a built-in Pull-Up/Down resistor on each pad. These pull-up/down resistors should be selected either pull-up or pull-down by configurable option first, and then can be controlled by users' program through RPC.
corresponding pad(s) to output mode.
PC is used to store the data contents for output.
get the stored data when corresponding bit of DPC is set as output mode, or will get the pad status if it is in input mode.
The corresponding pads are assigned for SPMC802B as following: (VDD = 5.0V) PIN PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 Rp 100K Up/Down@rpc7 100K Up/Down@rpc6 100K Up/Down@rpc5 100K Up/Down@rpc4 100K Up/Down@rpc3 100K Up/Down@rpc2 100K Up/Down@rpc1 100K Up/Down@rpc0 IN OUT 8/8mA 8/8mA 8/8mA 8/8mA 8/8mA 8/8mA 8/8mA 8/8mA Special Function IRQ2 interrupt input IRQ2 interrupt input IRQ2 interrupt input IRQ2 interrupt input IRQ2 interrupt input IRQ2 interrupt input IRQ2 interrupt input IRQ2 interrupt input
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SPMC802B
5.4. Port D Group
The I/O port D has 4 programmable I/Os that are controlled by data register PD, direction control register DPD, and pull-up/down resistance control register RPD. I/O attribute. DPD is used to control the pad There is a built-in Pull-Up resistor on each pad. These pull-up It is a write-only register. Reading PD will resistors can be controlled by users' program through RPD. Setting the bit(s) to '1' will enforce the get the stored data when corresponding bit of DPD is set as output mode, or will get the pad status if it is in input mode.
corresponding pad(s) to output mode.
PD is used to store the data contents for output.
The corresponding pads are assigned for SPMC802B as following: (VDD = 5.0V) PIN PD3 PD2 PD1 PD0 Rp 100K Up@rpd3 100K Up@rpd2 100K Up@rpd1 100K Up@rpd0 IN OUT 8/8mA 8/8mA 8/8mA 8/8mA Special Function
5.5. Interrupt
There are four kinds of interrupt, Software Interrupt, External Interrupt, Timer Interrupt, and Comparator interrupt. Each of the last three interrupts has individual status (occurred or not) and control (enable or not) registers, whereas Software Interrupt does not. In general, once an interrupt event occurs, the corresponding flag bit will be set. If the related interrupt control The The external interrupt IRQ0 supports interrupt-flag-bit auto-clearing function. It is activated only when interrupt event until the active level condition is removed. support edge trigger mode only. IRQ1 and IRQ2
channels of IRQ1 is disabled. When the auto-clearing function is activated, the flag of IRQ0 will be cleared automatically as soon as the interrupt vector is accessed. The user software in interrupt service routine does no need to check the flag because that flag bit has been cleared by hardware. source of the system. It is used to simplify the interrupt service routine only when the IRQ0 is the unique interrupt
bit is set to enable interrupt, an interrupt request signal will be generated and will be dealt with by CPU for service. prevent program from deadlock in interrupt service routine. Software interrupt is generated by the instruction BRK. The BRK interrupt flag bits must be cleared in the interrupt service routine to
If the Timer interrupts or Comparator
is an executable instruction interrupt; it is executed regardless of the state of the I-bit in the Processor Status Register Flag (inside CPU). It jumps to interrupt routine when BRK occurred. As with any instruction, interrupts pending during the previous instruction is served. External interrupts are coming from IRQ0, IRQ1, or IRQ2. These
interrupts are enabled with only IRQ0 being enabled as external interrupt source, the external interrupt event due to IRQ0 might be lost in case two interrupt events occur in the same time. interrupt channel, instead of using IRQ0, can solve it. To avoid However, the problem of IRQ0 loss, using IRQ1 or IRQ2 for external no matter the auto-clearing function of interrupt flag is functional, user software must clear the interrupt occurrence in the interrupt service routine. There is a new configurable option, named irqac, to be added for future supporting. This option can disable the auto-clearing The program tool to maintain the function of IRQ0 interrupt flag. body consistency will control it. In SPMC802B, IRQ0 is come from either PB5 with falling-edge trigger or group input PA3:0 with rising-edge trigger. PA3:0. IRQ1 is come from PA7. A configurable option is used to activate the group interrupt input on IRQ2 is come from external interrupt group input, PC7:0.
IRQ signals are combined with the configurable options and status/control registers to generate the interrupt events to CPU. For all IRQ channels, each channel has individual interrupt control or status bits. Once an external interrupt is occurred, the flag will The be set and stays at set unless user software clears the flag. enabled.
interrupt request signal will be generated in case of the interrupt is Channel IRQ0 has a configurable option used to set the The trigger mode can be trigger mode of the interrupt event.
selected as either edge trigger mode or level trigger mode. When the interrupt channel is enabled with edge trigger mode, an active transition edge on the external interrupt inputs will generate the interrupt. If the channel is enabled with level trigger mode, the active level of the external interrupt inputs will set the interrupt (c) Sunplus Technology Co., Ltd. Proprietary & Confidential 9
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SPMC802B
The Timer 1 interrupt and the Comparator interrupt will be described in detail in section Timer1 & Real Time Interrupt and section Comparator. The additional counting stages perform the Power On Reset (POR) cycle for clock settling down during power up, the Real Time Interrupt (RTI) function for timing applications, and watchdog Timer for function recovery. The POR and WDT functions are described in detail in section WDT & Reset. For Real Time Interrupt, there is a pre-scalar to perform the periodic timing events. if the interrupt is enabled. The pre-scalar is defined below. The timing events will set the flag and will generate interrupt for service
5.6. Timer1 & Real Time Interrupt
The clock input (XI/XO/R pins), fOSC, is internally divided by two to generate CPU clock, fCPU, for whole system. configurable option. Timer 1 clock, fTM1, is come from CPU clock with the divisor either 1 or 4 setting by The timer clock is fed into an 8-bit free-run Timer 1 Count Register (TCR1) is Once timer built as Timer 1 function.
used to read out the current counting value of Timer 1. generate interrupt for service if the interrupt input is enabled.
TCR1 is overflow, it will set the corresponding flag and will
rt1:0 00 01 10 11
RTI Rate Divisor 2048 4096 8192 16384 fTM1=fCPU/1* 2.048ms 4.096ms 8.192ms 16.384ms fTM1=fCPU/4* 8.192ms 16.384ms 32.768ms 65.536ms Divisor 16384 32768 65536 131072
WDT Reset time (=RTI/8) fTM1=fCPU/1* 16.384ms 32.768ms 66ms 131ms fTM1=fCPU/4* 66ms 131ms 262ms 524ms
Note1: In this example, the CPU clock is fCPU = 1.0MHz (fOSC = 2.0MHz). Note2: *The fTM1 is selected by configurable option fsel.
5.7. Timer2 & PWM
Timer 2 is a re-loadable 8-bit timer. and a control block. It consists with an 8-bit prescale counter, a pre-load register, an 8-bit count-up counter, The base clock input for Timer 2 fTIN2 can be It either from CPU clock fCPU, or from external clock through PB6. fTM2.
5.8. Comparator
SPMC802B is built with two channels of voltage Comparator. It can compare the external voltage input coming from PA4 or PA5 with the external voltage reference set up on PB0, or with the internal voltage reference (1.24V). These two channels Comparator can be enabled with the setup of comparison criterion and the reference source, and selectable interrupt input for event service. The input operating range of the Comparator is 0.2V to (VDD-0.2)V.
is fed into an 8-bit prescale counter to generate the Timer 2 clock, The prescalar for Timer 2 clock is set as 2 to the power of An 8-bit counter with a Pre-load Register consist the Timer 2 Count Register (TCR2) is used Once the Timer 2 clock is When Timer 2 rolls over the value.
main counter of Timer 2.
to set up the pre-load value in write mode and to read out the current counting value in read mode. enabled, main counter will count up.
5.9. WAIT & STOP Mode
There are two kinds of clock control mode supported by SPMC802B as WAIT mode and STOP mode. The WAIT mode function will disable CPU clock but leave the timer clock active, if the bit wait is set as '1'. Once the system being entered the WAIT mode, the activated interrupt events will recover the normal operation immediately from the next address of WAIT mode interrupt point. To confirm the interrupt events can wake up the CPU, the corresponding interrupt enable bits must be set before entering the WAIT mode. The STOP mode function will disable whole system clock, if the bit stop is set as '1'. Once the system being entered the STOP mode, only the activated external interrupt events (from I/Os) can 10 AUG. 07, 2002 Version: 1.0
from $FF to pre-load data, it generates overflow signal and reloads the pre-load data into the counting stage and counts up again. The overflow signal will also generate interrupt for service if the interrupt function is enabled. The PWM waveform generator consists with a 3-duty cycle PWM generator, a 64-duty cycle PWM generator, and a control block for PWM waveform output to PB7. The general I/O function on PB7 There are two will be disabled while the PWM output is enabled.
kinds of waveform output can be selected, fixed 3-duty cycle waveform output and programmable 64-duty cycle waveform output. The overflow signal of Timer 2, is the base clock of PWM It will feed into the 3-duty cycle waveform generator generator.
and the 64-duty cycle waveform generator. (c) Sunplus Technology Co., Ltd. Proprietary & Confidential
SPMC802B
recover the normal operation from the next address of STOP mode interrupt point with 1024 fTM1 clock cycle recovery time for stable oscillation. To confirm the external interrupt events can wake up the system, the corresponding interrupt enable bits must be set before entering the STOP mode. There are two write paths. One is come from direct write mode The purpose for the dual write The option incap is used to The indexed write for this Stack Limit Register (SLR), System Guard Register (SGR), System Control Register (SCR), and System Stop & Wait Register (SNW). The read of these registers uses direct access. A specific write cycle, named indexed write Reading the registers through page 0 addresses can get the contents directly. cycle, is implemented to have higher reliability of content updates. The indexed addresses for these registers are same as the direct addresses used in read cycle. through address $0008, another is come from indexed write mode through indexed address $08. paths is for backward compatibility.
5.11.1. Indexed write cycle
The procedure of indexed write cycle is formed with two consecutive write cycle of page 0. $003F, called write-data cycle, Only a write with address can program the reset $003E, called write-index cycle, followed with a write with address management registers. ROM area read cycles. The intersections in between these two If a ROM-write cycle or an access cycle
inhibit the STOP function coming from the direct write cycle of SNW to improve the system reliability. register will be described in detail later.
5.10. Reset
There are five kinds of reset resource for the system, Power On Reset (POR), External Reset (PB4), Low Voltage Reset (LVR), Watchdog Timer Reset (WDT), and Illegal Address Reset (IAR). These reset sources can be concluded as external events and internal events. The external events are come from the power The internal events are come from line, or external trigger event.
write cycles are allowed only for the code pre-fetches, means neither a ROM-read cycle nor a write-data cycle is executed after the write-index cycle, the indexed write cycle will be abnormal terminated without any data updates on these registers. To prevent abnormal termination of the indexed write cycle, programmers should handle the cycle much carefully. The interrupts should be disabled to prevent unpredicted intersections.
the program exceptions or internal software reset event.
5.11. Reset Management Registers
There are four registers implemented for reset event management,
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SPMC802B
6. ELECTRICAL CHARACTERISTICS
6.1. Item Definition
Symbol VIH VIL VTH SFV DFV Definition Input High Voltage Input Low Voltage Input Threshold Voltage Frequency Stability Frequency Deviation Symbol IOH IOL IZ RP Definition Output High Current (Source) Output Low Current (Sink) Output Leakage Current (Source) Pull-Up/Down Resistance
6.2. Absolute Maximum Rating
Characteristics Storage Temperature Operating Ambient Temperature Voltage Rating on Input Voltage Rating on VDD Output Voltage VOUT Symbol TSTR TOPR VIN Min. -40 0 -0.3 -0.3 0 Typ. Max. 125 70 VDD +0.3 7.0 VDD Unit C C V V V
For normal operational
Condition
Note: Stresses beyond those given in the Absolute Maximum Rating table may cause operational errors or damage to the device. conditions see AC/DC Electrical Characteristics.
6.3. Recommended Operating Conditions
Characteristics Operating Supply Voltage CPU Clock (Internal CPU clock) Power Consumption Power Down Current* Power Up Initial Voltage Power On Reset Time LVR Trigger Voltage Symbol VDD fCPU IDD IPD VINIT tPOR VLVR Min. 3.0 200K 50 Typ. 5.0 2.2 Max. 5.5 6.0M 10 0.5 Unit V Hz mA A V ms V VDD starts from VINIT VDD = 5.0V fCPU = 6.0MHz @ VDD = 5.0V VDD = 5.0V Condition
Note: The power-down current is measured in SLEEP mode with all I/O pins in hi-impedance state and tied to VDD or VSS.
6.4. PIN Attribute Description (VDD = 5.0V, TA = 0C~70C)
Mnemonic XI, XO Description Special Input Cell Pair for RC oscillation Symbol SFV DFV RP PA7:6 Input with Schmitt Trigger with Fixed Pull-Up R 8mA Open-Drain Output VIH VIL IOL IP PA5:0 PB7:6, 3, 0 PC7:0 Input with Pull-Up/Down option 8mA Output VIH VIL IOH IOL IP PB5 Input with Schmitt Trigger VIH Min. 2.0 8.0 3.5 8.0 8.0 2.4 Typ. 27 1.0 50 Max. 5.0 10 0.8 1.4 Unit % % K V V mA mA V V mA mA A V VOH = 2.4V VOL = 0.5V VIN = VDD or VSS VOL = 0.5V VIN = VSS Condition (f5.5V-f4.5V)/f5.0V * VDD = 5.0V fCPU_5.0V = 6.0MHz
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Mnemonic Description 8mA Open-Drain Output Symbol VIL IOL PB4 Input with Schmitt Trigger with Pull-Up R 8mA Output VIH VIL IOH IOL RP PB2:1 Input with Pull-Up R 20mA Open-Drain Output VIH VIL IOL IP PD3:0 Input with Pull-Up R 8mA Output VIH VIL IOH IOL IP All LVR I/O Port Hi-Z Leakage Threshold Voltage Operating Current Compare Input Hysteresis Voltage Input Common Mode Voltage CMRR Response Time** Compare Mode Change to Output Valid*** Operating Current IZ VLVR ILVR VHYS VICM CMRR tCV tCON ICMP Min. 8.0 2.0 8.0 8.0 70 3.5 20 3.5 8.0 8.0 2.1 0.2 50 Typ. 100 50 50 2.2 20 30 Max. 0.8 0.8 130 1.4 1.4 10 2.3 VDD -0.2 400 10 10 Unit V mA V V mA mA K V V mA A V V mA mA A A V A mV V dB ns s A per Channel VOH = 2.4V VOL = 0.5V VIN = VSS = 0V RP inactive Enable option VOL = 0.5V VIN = VSS = 0V VOH = 2.4V VOL = 0.5V VIN = VSS = 0V VOL = 0.5V Condition
Note1: *The frequency defined in this item is based on the CPU frequency. It is one-half of the oscillation frequency. Note2: ** Response time measured with one comparator input at VDD/2, while the other input transitions from VSS to VDD. Note3: *** tCON measured with Compare mode enable to output valid, while the internal reference voltage is selected from disable to enable and same setup of comparator inputs as the item tCV.
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SPMC802B
7. PACKAGE/PAD LOCATIONS
7.1. Package Information 7.1.1. PDIP 16
E1
D1
A2
c
L1 D1 E1 A2 L1 b c e Body Length Body Width Body Thickness Lead Length Lead Width Lead Thickness Lead Pitch PDIP-16-300
e Body Size Lead Size c e 10 100
b
D1 E1 A2 L1 b 750 250 130 115 18
All units are in mil. 1mil = 25.4m
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SPMC802B
7.1.2. PDIP 18
E1
D1
A2
c
L1 D1 E1 A2 L1 b c e Body Length Body Width Body Thickness Lead Length Lead Width Lead Thickness Lead Pitch PDIP-18-300
e Body Size Lead Size D1 E1 A2 L1 b c e 900 250 130 115 18 10 100 All units are in mil. 1mil = 25.4m
b
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SPMC802B
7.1.3. PDIP 20
E1
D1
A2
c
L1 D1 E1 A2 L1 b c e Body Length Body Width Body Thickness Lead Length Lead Width Lead Thickness Lead Pitch PDIP-20-300
e Body Size Lead Size
b
D1 E1 A2 L1 b c e 1020 250 130 115 18 10 100 All units are in mil. 1mil = 25.4m
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SPMC802B
7.1.4. PDIP 24
E1
D1
A2
c
L1 D1 E1 A2 L1 b c e Body Length Body Width Body Thickness Lead Length Lead Width Lead Thickness Lead Pitch PDIP-24-300
e Body Size D1 E1 1245 250 A2 130 L1 115 Lead Size b 18 c 10 e 100
b
All units are in mil. 1mil = 25.4m
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AUG. 07, 2002 Version: 1.0
SPMC802B
7.1.5. PDIP 28 (300mil)
E1
D1
A2
c
L1 D1 E1 A2 L1 b c e Body Length Body Width Body Thickness Lead Length Lead Width Lead Thickness Lead Pitch PDIP-28-300
e Body Size D1 1388 E1 290 A2 130 L1 115 Lead Size b 18 c 10 e 100
b
All units are in mil. 1mil = 25.4m
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AUG. 07, 2002 Version: 1.0
SPMC802B
7.1.6. PDIP 28 (600mil)
E1
D1
A2
c
L1 D1 E1 A2 L1 b c e Body Length Body Width Body Thickness Lead Length Lead Width Lead Thickness Lead Pitch PDIP-28-600 PDIP-28-300
e Body Size D1 1450 1388 E1 550 290 A2 150 130 L1 100 115 Lead Size b 18 c 10 e 100
b
All units are in mil. 1mil = 25.4m
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AUG. 07, 2002 Version: 1.0
SPMC802B
7.1.7. PDIP 32 (600mil)
E1
D1
A2
c
L1 D1 E1 A2 L1 b c e Body Length Body Width Body Thickness Lead Length Lead Width Lead Thickness Lead Pitch PDIP-32-600
e Body Size E1 550 Lead Size b c 18 10
b
D1 1650
A2 150
L1 100
e 100
All units are in mil. 1mil = 25.4m
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AUG. 07, 2002 Version: 1.0
SPMC802B
7.1.8. SOP 24 (300mil)
D
E
X
c
y
H
24
13
A2
A1
A
pin 1 index
detail X
L
L1
1
e
12
b
Symbol A A1 A2 b c D E e H L L1 y
Dimension in mm Min. 2.362 0.102 15.215 7.391 10.008 0.406 0
0
Dimension in inch Max. 2.642 0.305 15.596 7.595 10.643 1.270 0.102 8
0
Typ. 2.515 0.406 0.254 15.240 7.493 1.270 10.312 0.889 -
Min. 0.093 0.004 0.599 0.291 0.394 0.016 0
0
Typ. 0.099 0.016 0.010 0.600 0.295 0.050 0.406 0.035 -
Max. 0.104 0.012 0.614 0.299 0.419 0.050 0.004 8
0
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AUG. 07, 2002 Version: 1.0
SPMC802B
7.1.9. SOP 28 (300mil)
D E X
c y H
28
15
A2
A1
A
pin 1 index detail X
L
L1
1 e b
14
Symbol A A1 A2 b c D E e H L L1 y
Dimension in mm Min. 2.362 0.102 17.704 7.391 10.008 0.406 0
0
Dimension in inch Max. 2.642 0.305 18.110 7.595 10.643 1.270 0.102 8
0
Typ. 0.406 0.254 1.270 -
Min. 0.093 0.004 0.697 0.291 0.394 0.016 0
0
Typ. 0.016 0.010 0.050 -
Max. 0.104 0.012 0.713 0.299 0.419 0.050 0.004 8
0
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AUG. 07, 2002 Version: 1.0
SPMC802B
7.1.10. SOP 28 (330mil)
D E X
c y H
28
15
A2
A1
A
pin 1 index detail X
L
L1
1 e b
14
Symbol A A1 A2 b c D E e H L L1 y
Dimension in mm Min. 0.102 2.362 0.355 0.203 8.280 1.118 11.506 1.499 0.711 0
0
Dimension in inch Max. 2.845 2.616 0.508 0.356 18.618 8.534 1.422 12.116 1.905 1.117 0.102 10
0
Typ. 2.489 0.406 0.254 18.110 8.407 1.270 11.811 0.914 1.702 -
Min. 0.004 0.093 0.014 0.008 0.326 0.044 0.453 0.028 0.059 0
0
Typ. 0.098 0.016 0.010 0.713 0.331 0.050 0.465 0.036 0.067 -
Max. 0.112 0.103 0.020 0.014 0.733 0.336 0.056 0.477 0.044 0.075 0.004 10
0
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AUG. 07, 2002 Version: 1.0
SPMC802B
7.1.11. SOP 32 (445mil)
D E X
c y H
30
17
A2
A1
A
L pin 1 index detail X
L1
1 e b
16
Symbol A A1 A2 b c D E e H L L1 y
Dimension in mm Min. 0.102 2.565 0.356 0.152 20.142 11.176 1.118 13.868 0.584 1.194 0
0
Dimension in inch Max. 2.997 2.819 0.508 0.305 20.752 11.430 1.422 14.376 0.991 1.600 0.102 10
0
Typ. 2.692 0.406 0.203 20.447 11.303 1.270 14.122 0.787 1.397 -
Min. 0.004 0.101 0.014 0.006 0.793 0.440 0.044 0.546 0.023 0.047 0
0
Typ. 0.106 0.016 0.008 0.805 0.445 0.050 0.556 0.031 0.055 -
Max. 0.116 0.111 0.020 0.012 0.817 0.450 0.056 0.566 0.039 0.063 0.004 10
0
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SPMC802B
7.2. Ordering Information
Product Number SPMC802B-C SPMC802B-PD03 SPMC802B-PD04 SPMC802B-PD05 SPMC802B-PD06 SPMC802B-PD08 SPMC802B-PD09 SPMC802B-PD11 SPMC802B-PS04 SPMC802B-PS05 SPMC802B-PS06 SPMC802B-PS08 Package Type Chip form Package form - PDIP 16 Package form - PDIP 18 Package form - PDIP 20 Package form - PDIP 24 Package form - PDIP 28 (300mil) Package form - PDIP 28 (600mil) Package form - PDIP 32 (600mil) Package form - SOP 24 (300mil) Package form - SOP 28 (300mil) Package form - SOP 28 (330mil) Package form - SOP 32 (445mil)
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AUG. 07, 2002 Version: 1.0
SPMC802B
8. DISCLAIMER
The information appearing in this publication is believed to be accurate. Integrated circuits sold by Sunplus Technology are covered by the warranty and patent indemnification provisions stipulated in the terms of sale only. SUNPLUS makes no warranty, express, statutory implied or by description regarding the information in this publication or FURTHERMORE, SUNPLUS MAKES NO WARRANTY OF SUNPLUS reserves the right to halt production or alter the specifications and regarding the freedom of the described chip(s) from patent infringement. MERCHANTABILITY OR FITNESS FOR ANY PURPOSE. prices at any time without notice. publication are current before placing orders.
Accordingly, the reader is cautioned to verify that the data sheets and other information in this Products described herein are intended for use in normal commercial applications. Please note that application circuits
Applications involving unusual environmental or reliability requirements, e.g. military equipment or medical life support equipment, are specifically not recommended without additional processing by SUNPLUS for such applications. illustrated in this document are for reference purposes only.
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AUG. 07, 2002 Version: 1.0
SPMC802B
9. REVISION HISTORY
Date AUG. 07, 2002 Revision # 1.0 Original Description Page 27
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AUG. 07, 2002 Version: 1.0

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